The present invention generally relates to analog/digital integrated subscriber circuits, and more particularly to an analog/digital integrated subscriber circuit which is applicable to either an analog subscriber line or a digital subscriber line.
In many situations, analog subscriber lines and digital subscriber lines are connected to the same switching system, and an exclusive subscriber circuit is provided with respect to each of the analog subscriber line and the digital subscriber line. Accordingly, when an analog subscriber terminal is replaced by a digital subscriber terminal, for example, it is necessary to replace the subscriber circuit in the switching system or to change the connection in the switching system. In view of the above, it is conceivable to use a common subscriber circuit as the subscriber circuit which connects the analog subscriber line and the subscriber circuit which connects the digital subscriber line, however, no concrete structure has been proposed to realize such a conceivable common subscriber circuit.
FIG. 1 shows an example of a conventional analog subscriber circuit. FIG. 1 shows a subscriber line 100, a hybrid circuit (HYB) 101 which makes a 2-wire/4-wire conversion, a power supply part 102, a pre-filter (PREFIL) 103, a post-filter (PSTFIL) 104, an analog-to-digital (A/D) converter 105, a digital signal processor (DSP) 106, a linear p converter (L/.mu.) 107, a .mu. linear converter (.mu./L) 108, a network interface circuit (NIF) 109, a .SIGMA./.sub..DELTA. modulator (SDMA) 110 which converts an analog signal into a digital signal by a .SIGMA./.sub..DELTA. modulation, a decimation filter (DFIL) 111, a .SIGMA./.sub..DELTA. modulator (SDMD) 112 which converts a digital signal into an analog signal by a .SIGMA./.sub..DELTA. modulation, an interpolation filter (IFIL) 113, a balancing network (BN) 114, a bandpass filter (BPF) 115, a lowpass filter (LPF) 116, and a digital-to-analog (D/A) converter 117.
The power supply part 102 has a constant voltage supplying characteristic for supplying a power supply voltage of 48 V, for example, with respect to the subscriber line 100. An analog voice signal from the subscriber line 100 is supplied to the A/D converter 105 via the hybrid circuit 101 and the pre-filter 103, and is converted into a digital signal. The digital signal is supplied to the DSP 106 which realizes processing functions such as filtering by the BPF 115, the LPF 116 and the balancing network 114. The linear p converter 107 converts the digital signal from the DSP 106 into a 64 kbps digital voice signal having an 8 bits/sample structure according to the .mu. compression and expansion rule, and transfers the digital voice signal to a channel switch side via the network interface circuit 109.
On the other hand, the digital voice signal which is in conformance with the .mu. compression and expansion rule and is input to the network interface circuit 109 is converted into a linear digital voice signal by the .mu. linear converter 108. The linear digital voice signal is passed through the LPF 116 of the DSP 106, and is input to the D/A converter 117 which is made up of the interpolation filter 113 and the .SIGMA./.sub..DELTA. modulator 112. Hence, the linear digital voice signal is converted into an analog voice signal and is transmitted to the subscriber line 100 via the post-filter 104 and the hybrid circuit 101.
FIG. 2 shows an example of a conventional digital subscriber circuit. FIG. 2 shows a subscribe line 120, a hybrid circuit (HYB) 121, a power supply part 122, a pre-filter (PREFIL) 123, an A/D converter 124, a feed forward equalizer (FFE) 125, a decision feedback equalizer (DFE) 126, an automatic gain control (AGC) part 127, a digital phase locked loop (DPLL) circuit 128, a network interface circuit (NIF) 129, an AMI decoder (AMI) 130, a line driver (DRV) 131, a sequence controller (SEQ) 132, a .SIGMA./.sub..DELTA. modulator (SDM) 133, and a decimation filter (DFIL) 134.
The power supply part 122 has a constant current characteristic for supplying a power supply current of 39 mA, for example, with respect to the subscriber line 120. The sequence controller 132 carries out a training control when making a call setup between the sequence controller 132 and a digital subscriber terminal which is connected to the subscriber line 120, via a path which is not shown in FIG. 2. A waveform equalization is made by the feed forward equalizer 125 and the decision feedback equalizer 126, and a function of the feed forward equalizer 125 is selected by the AGC part 127, so that a digital signal having a desired level is transferred to the channel switch side via the network interface circuit 129.
FIG. 3 is a diagram for explaining the operation of a conventional DSP, such as the DSP 106 of the analog subscriber circuit described above. In FIG. 3, a computing block 141, an address computing block 132, an internal memory (IRAM) 143, a program sequence control block 144, a special register/counter block 145 and an input/output (I/O) interface block 146 are coupled via an internal bus 147.
The computing block 141 includes an arithmetic logic unit ALU, a multiplier MPY, registers A, B and P, and accumulators C and D, and a multiplication is carried out by the multiplier MPY and various operations are carried out by the arithmetic logic unit ALU. In addition, the address computing block 142 includes an address computing unit AALU, registers X0, B0, X1, B1, X2, VSM, PAG and EAR, and a direct memory access (DMA) counter DMC. For example, it is possible to obtain an effective address from a result of additions of the contents of the base registers B0 and B1 and the index registers X0 and X1 and an offset.
In this particular case, the internal memory 143 is made of a 3-port random access memory (RAM). The program sequence control block 144 includes an instruction memory IROM, an instruction register IR, a program counter PC, a decoder DEC, loop counters C0 and C1, and a repeat counter RPC. An address is loaded by successively incrementing the program counter PC or by a branch instruction, interrupt or the like, and an instruction is read from the instruction memory IROM and set in the instruction register IR, so as to control various parts based on a decoding carried out by the decoder DEC.
The special register/counter block 145 includes a timer counter TIM, a mode setting register MOD, an interrupt mask register MASK, a status register ST, and a register group Reg.File. The I/O interface block 146 includes serial input registers SI0 and SI1, serial output registers SO0 and SO1, a parallel input register PI, a parallel output register PO, a parallel address input register PIA, a parallel address output register POA, and a unit number register PAD.
Due to the progress made in the semiconductor integration technology, the size of various parts of the system have been reduced. For example, the analog subscriber circuit is formed as a single package with respect to eight subscribers, and the digital subscriber circuit is formed as a single packet with respect to four subscribers. As a result, the size of the system as a whole can be reduced. However, if one of the eight subscribers changes his analog subscriber terminal to a digital subscriber terminal, it becomes necessary to modify the position of this subscriber with respect to the analog subscriber circuit. In addition, if a fault is generated in the structure of the analog subscriber circuit related to one of the eight subscribers of the analog subscriber circuit, it becomes necessary to forcibly disconnect the remaining seven subscribers when replacing the analog subscriber circuit by a new package of the analog subscriber circuit. As a result, there was a problem in that the service provided with respect to the subscribers becomes poor.
In order to solve the problem described above, it is conceivable to provide a single package of the subscriber circuit with respect to each subscriber. In this conceivable case, when replacing the analog subscriber terminal by a digital subscriber terminal or vice versa or, when a fault is generated in the subscriber circuit, it is simply necessary to replace one package of the subscriber circuit. However, it becomes necessary to provide in advance a large number of analog subscriber circuits and a large number of digital subscriber circuits, and the system as a whole becomes expensive. Further, if a large number of subscribers are connected to the switching system, it is not easy to replace the packages without an error.
Alternatively, it is conceivable to use a common subscriber circuit as the analog subscriber circuit and the digital subscriber circuit. However, the power supply part 102 of the analog subscriber circuit is designed to supply a constant voltage of -48 V, for example, to the subscriber line 100. On the other hand, the power supply part 122 of the digital subscriber circuit is designed to supply a constant current of 39 mA, for example, to the subscriber line 120. If the impedance of the subscriber liner 120 is large, the output voltage of the power supply part 122 rises, but a maximum output voltage is set to approximately 60 V, for example. Therefore, due to the different characteristics of the power supply parts 102 and 112, it was impossible to use a common subscriber circuit as the analog subscriber circuit and the digital subscriber circuit.
On the other hand, in the analog subscriber circuit, the sampling frequency is 8 kHz, for example, and voice signal processings such as filtering and computing may be carried out by the DSP. But in the digital subscriber circuit, the sampling frequency must be 320 kHz, for example, when a ping-pong transmission system is employed, and it is not possible to simply apply the DSP of the analog subscriber circuit to the digital subscriber circuit. Furthermore, when an echo cancelling system is employed, it is necessary to have a large equalizing capability with respect to the intersymbol interference component so as to cope even with a 2-B 1-Q code which includes a D.C. component. Therefore, compared to the DSP of the analog subscriber circuit, the DSP of the digital subscriber circuit must operate at a high speed, and there was a problem in that the digital subscriber circuit becomes expensive.